1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a bit line of a semiconductor device.
2. Description of the Related Art
Generally, in memory cells of semiconductor devices, a bit line is known as a signal-transmission passage between components constituting unit memory devices which can store 1-bit unit data.
FIG. 1 illustrates a bit line formed by a method for fabricating a bit line of a semiconductor device in accordance with conventional methods.
Referring to FIG. 1, in fabricating the bit line of a semiconductor device, a first interlayer dielectric film 110 is formed on a semiconductor substrate 100 having gates (not shown) and landing plugs (not shown) formed thereon. Next, a portion of the first interlayer dielectric film 110 is etched such that the upper parts of the landing plugs are exposed, thereby forming a bit line contact hole (not shown). A barrier metal film (not shown) is formed inside the bit line contact hole. Next, a conductive material (not shown) is formed such that the bit line contact hole is embedded, thereby forming a bit line contact (not shown). Next, a bit line-forming material (not shown), e.g., tungsten and nitride material, is deposited on the bit line contact and first interlayer dielectric film 110.
The bit line-forming material is then etched to overlap with the bit line contact, thereby forming bit line stacks 120 in which, for example, tungsten 125 and a hard mask nitride film 127 are sequentially stacked. Next, bit line spacers 130 are formed on the sidewalls of the bit line stacks 120. The bit line spacers 130 may be formed from a nitride film, which has high tensile stress. Then, an oxide film (not shown), which is a second interlayer dielectric film, is formed on the first interlayer dielectric film 110, via a high density plasma (HDP) process, such that the gap between the bit line stacks 120 is embedded. The oxide film, formed by the high density plasma (HDP) process, has compression stress.
The bit line of the semiconductor device in accordance with conventional methods suffer from collapse of the bit line stacks 120 due to different properties between the bit line spacer 130 and the oxide film in the course of embedding the oxide film, as the second interlayer dielectric film, during a high density plasma (HDP) process. Bit line spacers 130 exhibit high tensile stress, while the oxide film, as the second interlayer dielectric film, exhibits compression stress. The different types of stress results in a collapse of the bit line stacks 120, as represented by ‘A’ in FIG. 1.
Such stress-induced collapse of the bit line stacks 120 becomes more severe as the semiconductor device is highly integrated. For example, a conventional 80 nm-sized semiconductor device can resist stress with the second interlayer dielectric film by securing a final critical dimension of about 70 nm of the bit line stacks 120. As the dimensions of semiconductor devices have recently been reduced to 65 nm due to high degree of integration thereof, a final critical dimension of the bit line stacks is sharply decreased to 30 nm. Consequently, capability of the bit line stacks to withstand stress with the second interlayer dielectric film is lowered, thereby resulting in a collapse thereof, which in turn leads to a short-circuit with adjacent bit line stacks, thus deteriorating characteristics of the devices. As such, it is difficult to fabricate high-reliability devices.